`timescale 1ns/1ps
`default_nettype none
module dmem #(
    parameter DEPTH_WORDS = 256
)(
    input  wire        clk,
    input  wire        memread,
    input  wire        memwrite,
    input  wire [31:0] addr,     // byte address
    input  wire [31:0] wdata,
    output wire [31:0] rdata
);
    reg [31:0] mem [0:DEPTH_WORDS-1];

    assign rdata = memread ? mem[addr[31:2]] : 32'b0;

    always @(posedge clk) begin
        if (memwrite) mem[addr[31:2]] <= wdata;
    end
endmodule

